1. Field of the Invention
The invention relates to an electrostatic discharge (ESD) protection device, and more particularly to an ESD protection device for high voltages.
2. Description of the Related Art
As semiconductor manufacturing develops, electrostatic discharge (ESD) protection has become one of the most critical reliability issues for integrated circuits (IC). Several ESD test modes, such as machine mode (MM) or human body mode (HBM), have been proposed to imitate the circumstances under which an ESD event may occur. The ability to withstand certain levels of ESD is essential for successful commercialization of an IC.
ESD protection circuits are generally located at input/output ports or between power rails of ICs, to release electrostatic stress before the electrostatic stress damages interior or core electronic circuits therein. ESD protection circuits are typically designed to be switched off during common/normal signal operation and switched on during an ESD event to release accumulated electrostatic charge.
To sustain a high voltage, the conventional ESD element is typically constituted by a high voltage element of a corresponding circuit. However, the track of the high voltage element affects the distribution of the electric field. Thus, a corresponding circuit may be damaged.
The conventional method to solve the ESD problem for high voltages is to design a terminal of the high voltage element into a separate pad. However, the ESD element also requires a separate pad. Thus, complexity of the circuit layout is increased and size of the corresponding circuit is also increased.